Analogue to Digital (ADC) board design
When developing custom boards with Analogue inputs there are many pitfalls if you are not extremely careful.
Customers often specify only the clock rate (sampling speed) and number of bits (resolution), but that is far from enough information in order to get the results that you want.
Analogue to Digital Converters take samples of analogue signals at particular points in time, and output a digital snapshot of the voltage of that signal, at that time. In this way a series of values are obtained, that represent the voltage level at particular time points.
A clock signal is used to determine when the samples are taken, so the time points where the sample is taken are controlled by the clock signal.
Different applications might require different sample rates according to the information content of the input signal. Often the sample rate also determines parameters in the following signal processing, for example the frequency of the bins of an FFT, or the cut-off frequency of a digital filter.
The digital samples represent the voltage, sampled in each sample of the clock signal (normally at the rising edge). The resolution of the ADC, in bits (N), describes the number of voltage steps that can be represented by the ADC (2^N) in each sample. The voltage swing that can be accepted by the ADC (V) is divided into that number of steps each represented by one of the possible digital numbers. The size of the steps between the digital values can then be calculated by V/(2^N).
As with everything in life, the ADC process is not perfect. As soon as you digitise a signal you have introduced errors, because of the finite number of voltage and time steps that you have broken your signal into.
Signal to Noise Ratio (SNR)
The best way to represent the effect of these (and other) errors is as a Signal to Noise Ratio (SNR).
SNR is normally described in dBs, which is 10log(ratio of powers) or 20log(ratio of voltage), or the signal (the part you want) to the noise (the unwanted part).
The more bits resolution your ADC has, the lower the noise introduced by the digitisation process is when compared to the Signal, so the higher the SNR (theoretically). The theoretical best SNR of an ADC is approximately 6dB per bit of the ADC. No ADC component is perfect; they all introduce some further noise into the system. So it is important to consider the SNR specification of the components when selecting one to use. Of course the manufacturers measure of SNR for their data sheet is going to be the best possible reflection of their part, so the tests will make certain assumptions.
Then the use of the components on a real board will introduce further noise, adversely affecting the system SNR. Some noise will come from unavoidable sources like thermal noise etc, but there are other sources that can be more dominant.
Spurious Free Dynamic Range (SFDR)
Because of the sampling process, and imperfections of the devices, sampling of the signal introduces some frequency information into the samples that was not present in the original signal.
SFDR is a ratio of the signal (when set to the largest that can be digitised) to the next highest level signal frequency that is present in the samples.
It is expressed in dBs just like SNR, and is another important measure of the quality of the system.
Usually the frequency of the next highest frequency point is a harmonic of the signal, but it might not be. So it is interesting to know what is the highest level harmonic frequency also.
Sample Clocks and Jitter
The timing of the conversion of samples is determined by the Clock signal. For most users the frequency of the sampling is all that they care about, but it shouldn’t be!
Clock jitter is vitally important, as by sampling the signal at the wrong time, it introduces an error (the difference from the actual sample, to the value at the proper sampling point) which appears as noise in the samples. Unless clock jitter is very tightly controlled, the SNR of the system will be severely degraded.
The SNR (due to clock jitter) can be calculated as -20log (2*pi*Finput*tjitter).
With higher and higher sample frequencies, you can expect to digitise higher and higher frequencies of input signal. This makes the jitter of the clock become more and more important.
Just to show how important, lets look at a made up example.
A 12 bit ADC has a maximum theoretical SNR of 72dB.
If we are trying to digitise a 100Mhz signal, with a clock having 1ps of jitter, the SNR limit due to that jitter is 64dB. So just 1 picosecond of clock jitter can be more of a limit than having 12 bits of your ADC.
For that reason we like to use special clock generation components that use Phase Locked Loops to reduce the clock jitter as much as possible, to preserve the SNR of the system.
Some applications may have a system clock that the samples need to be synchronised to, in which case an external clock input is necessary. Jitter is harder to control here, but putting the external clock through the same Phase Locked Loop circuitry will help to improve (reduce) the jitter.
Differential Vs Single ended
Most high specification converter ICs offer differential signals.
There are several reasons to use differential signalling :-
- Rejection of common mode noise – any noise received on both of the differential inputs cancels out
- Removal of the need for an accurate common ground between the converter chip and the signal source, as the signal content is not referenced to Gnd but to each other.
- Better balance of currents flowing in and out of the chip, so less problem with Ground Bounce
- Higher effective signal swing – allowing a better SNR
The converter chips operate on certain power supply levels – often 3.3V or less to GND. This means that their circuitry cannot operate outside of these limits, and in the real world cannot operate at the limits either. This limits the voltage swing of the signal. Using two differential signals allows each of them to have that voltage swing – effectively doubling the signal level. This has a knock on effect in Signal to Noise levels because of that doubled signal – better possible SNR.
The graph shows that although each signal swings by 2 volts, the difference changes from +2V to –2V –a swing of 4volts.
To gain the advantages of the differential signalling, both signals need to be connected to the user equipment. If the user doesn’t have a way of connecting a differential signal, and does not want to convert it, it is possible to connect a single ended signal directly. Here the other signal simply remains constant at the centre point of the voltage swing.
Here the signal still swings 2 volts, but the difference, is also 2 volts. So the signal level is reduced and hence so is the Signal to Noise ratio, as the noises in the system are not changed.
Use of single ended signals also cancels out the other advantages of differential signals listed above When using a differential port in a single ended way, simply leave the other connection unconnected.
Power supply noise
The ADC device and any connected amplifiers, voltage references etc, will work most effectively
with a power supply that has been designed to have minimal noise. Often this is interpreted as the need to have separate “quiet” power supply circuits for these analogue components. Actually if your board is designed so that it is properly bypassed (also sometimes called decoupled), then at all frequencies other than DC, your power supplies will have a really low impedance to GND and hence to each other. Then any high frequency noise on any of the power supplies is automatically present on all of the other supplies.
So to have the best performance for your ADC system, all of the power supplies on your board must be designed for low noise and ripple.
Testing your ADC performance
Surprisingly, after struggling to achieve the very best performance from your ADC board design, when you come to test what you have achieved, you have a whole new set of problems.
Your expensive signal generator that sits on your test bench almost certainly outputs more noise than you would like to have in your ADC system. Dotstar have signal generators that have been bought specifically with their noise performance in mind, but still can design ADC boards with better performance. In these cases very aggressive filters must be added between the signal generator and the board under test, to remove the harmonics from the signal.
If you need to develop a board with high performance ADC interfaces just contact us for help.
We can also help with the manufacture and test of your system if you would like.